1. Technical Field
The present invention relates generally to fill tiling patterns for an integrated circuit.
2. Background Art
Current integrated circuit (IC) manufacturing techniques benefit from a uniform density of wiring or conductors within a layer. For example, uniform density is required to prevent different amounts of wear across a plane during chemical mechanical polishing. To provide uniform density, various techniques for filling of empty spaces have been developed. See, for example, U. S. Pat. Nos. 5,278,105 (Eden et al.), 5,341,310 (Gould et al.) or 5,923,563 (Lavin et al.).
One challenge in providing uniform density of wiring within a plane is addressing the effect of fill tiling patterns on the electrical properties, i.e., fill tiles acting as fringe capacitance, on an adjacent wire. In particular, fill tiles add complexity to the electrical analysis of the circuit because each shape represents a floating conductor coupled by capacitors to the wire. As a result, the fill tiles change the overall capacitance between the connected wires of the circuit, and modify the electrical analysis result. Conventionally, fill tile patterning is addressed by predicting the electrical impact of the fill tiles relative to all electrically significant shapes. By mathematically accounting for the impact of the fill tiles, new capacitances between the connected circuits can be established and then fitted to modified expressions. One conventional technique for predicting the impact of fill tiles is to assume a uniform fill tile environment around shapes based on the predicted behavior of the fill tile pattern creation program. This technique is used because it takes into account the fill tile pattern without increasing the amount of computational resources required to analyze the layout compared to actually adding the fill tiles to the layout.
This uniform fill tile pattern assumption, historically, yields acceptable results because of the orthogonal nature of the wiring and the use of square fill tiles. That is, most wiring has an orthogonal layout (i.e., wires meet at right angles) and the fill tiles are oriented parallel thereto. Advancements in processing technology, however, are now making mixed non-orthogonal and orthogonal wiring patterns possible. Unfortunately, the provision of mixed orthogonal and non-orthogonal wiring with orthogonal fill tile patterns makes the fill tile environment non-uniform relative to the wiring. Accordingly, consistent assumptions about the impact on electrical properties of the fill tile patterns are no longer possible. To illustrate, FIG. 1 shows an IC including orthogonal and non-orthogonal wiring and an orthogonal fill tiling pattern throughout. In this situation, one can assume for analysis a uniform environment across much of the IC because of the orthogonal nature of the wiring and fill tiles. However, because the distance of the tiling pattern from the non-orthogonal (diagonal) wire varies along the wire's length, a number of additional parameters for each non-orthogonal wire segment must be known in order to make valid assumptions. For example, the precise length, the corresponding periodicity and angle of the fill, and the impact on the electrical properties must be ascertained for each segment of non-orthogonal wire. Consideration of all of these parameters makes analysis of the impact of the orthogonal fill tiling on the adjacent non-orthogonal wiring impracticable.
In view of the foregoing, there is a need in the art for a method for providing a substantially uniform density and electrical characteristics for an integrated circuit having mixed orthogonal and non-orthogonal electrical structure.